This invention relates to an integrated circuit for processing signals at high speed by decreasing a parasitic capacity in a common bus line.
A bus line system is generally adopted for a highly integrated circuit to effectively reduce an area occupied by wiring. With the bus line system, the peripheral circuits are grouped into blocks. These circuit blocks are connected to a given number of common bus lines through the corresponding input-output circuits (hereinafter referred to as "I/O circuits"). Data are transmitted between the respective peripheral circuits through the common bus lines. Therefore, as compared with a system using independent lines for the respective circuit blocks, the bus line system can noticeably decrease the number of lines, thereby simplifying arrangement of lines and preventing an increase in their number.
With the above-mentioned bus line system, the bus lines and diffused regions constituting I/O circuits are connected by diffused lines. Consequently, a difficulty arises in that the junction capacity possessed by the diffused regions tends to be parasitically accumulated in the bus line.
FIG. 1 illustrates the manner in which a parasitic capacity is accumulated in a bus line used with a conventional bus line system. FIG. 1 shows in enlargement part of a junction of a diffused line and bus line used in the prior art integrated circuit provided with four common bus lines. The common bus lines 10.sub.1 to 10.sub.4 are formed of aluminum and are arranged in parallel at a prescribed interval. The common bus lines 10.sub.1 to 10.sub.4 are set on diffused lines 12.sub.1 to 12.sub.4 at right angles. Reference numerals 13.sub.1 to 13.sub.4 denote the regions in which the diffused lines 12.sub.1 to 12.sub.4 and bus lines 10.sub.1 to 10.sub.4 contact each other. As a result, the capacities of the diffused lines 12.sub.1 to 12.sub.4 and the capacities 14.sub.1 to 14.sub.4 of diffused I/O regions (not shown) become parasitic on the common bus lines 10.sub.1 to 10.sub.4.
Where an integrated circuit is enlarged in scale and consequently circuit blocks increase in number, then I/O circuits connected to common bus lines also have a large number. Therefore, a parasitic capacity in the common bus line increases. The increased parasitic capacity causes the common bus line to have a large time constant (.tau.=CR). Accordingly, transmission of a signal through such common bus line is prominently delayed. This event presents difficulties in processing data at high speed by a one chip LSI circuit.
For resolution of the above-mentioned drawback, a method has been proposed which is intended to elevate the conductivity of diffused I/O lines. However, this method results in an increase in a total area of diffused lines, and consequently a decline in an integration density per unit area. Therefore, said method has proved practically unsuitable for high integration.